VeriPy: A Python-Powered Framework for Parsing Verilog HDL and High-Level Behavioral Analysis of Hardware-Reference-Cited by-同舟云学术

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VeriPy: A Python-Powered Framework for Parsing Verilog HDL and High-Level Behavioral Analysis of Hardware

Published:2024-04-19 Issue: Volume: Page:1-6
ISSN:
Container-title:2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS)
language:
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Author:

Rashid Md Imtiaz¹,Schaefer B. Carrion¹

Affiliation:

1. The University of Texas at Dallas,Department of Electrical and Computer Engineering

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10539858/10539859/10539889.pdf?arnumber=10539889

Reference16 articles.

1. Automated HW/SW Co-Design of DSP Systems Composed of Processors and Hardware Accelerators;Roane;Cadence, Tech. Rep.,2023

2. Qualcomm: Designing ASIC IP at a higher level of abstraction;David;Qualcomm, Tech. Rep.,2021

3. Working smarter, not harder: NVIDIA closes design complexity gap with HLS;Sijstermans;NVidia, Tech. Rep.,2021

4. A method to abstract RTL IP blocks into C++ code and enable high-level synthesis

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