Automatic Generation of Architecture-Level Models from RTL Designs for Processors and Accelerators
Author:
Affiliation:
1. Princeton University,Princeton,USA
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9774496/9774497/09774527.pdf?arnumber=9774527
Reference19 articles.
1. Automatic Abstraction of RTL IPs into Equivalent TLM Descriptions
2. A Methodology to Recover RTL IP Functionality for Automatic Generation of SW Applications
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