Pipeline gating

Author:

Manne Srilatha1,Klauser Artur2,Grunwald Dirk2

Affiliation:

1. University of Colorado, Dept. of Electrical and Computer Engineering, Boulder, CO

2. University of Colorado, Department of Computer Science, Boulder, CO

Publisher

Association for Computing Machinery (ACM)

Cited by 55 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. FOCAL: A First-Order Carbon Model to Assess Processor Sustainability;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

2. RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining;IEICE Transactions on Information and Systems;2020-12-01

3. AUDITOR: A Stage-Wise Soft-Error Detection Scheme for Flip-flop Based Pipelines;Lecture Notes in Computer Science;2017

4. Improvement of Renamed Trace Cache through the Reduction of Dependent Path Length for High Energy Efficiency;IEICE Transactions on Information and Systems;2016

5. An Overview of Architecture-Level Power- and Energy-Efficient Design Techniques;Advances in Computers;2015

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