RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining-Reference-Cited by-同舟云学术

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining

Published:2020-12-01 Issue:12 Volume:E103.D Page:2494-2503
ISSN:0916-8532
Container-title:IEICE Transactions on Information and Systems
language:en
Short-container-title:IEICE Trans. Inf. & Syst.

Author:

MIYAZAKI Hiromu¹,KANAMORI Takuto¹,ISLAM Md Ashraful¹,KISE Kenji¹

Affiliation:

1. School of Computing, Tokyo Institute of Technology

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Artificial Intelligence,Electrical and Electronic Engineering,Computer Vision and Pattern Recognition,Hardware and Architecture,Software

Link

https://www.jstage.jst.go.jp/article/transinf/E103.D/12/E103.D_2020PAP0015/_pdf

Reference28 articles.

1. [1] RISC-V Foundation, “RISC-V | Instruction Set Architecture (ISA).” https://riscv.org/.

2. [2] Xilinx, MicroBlaze Processor Reference Guide, v2018.2 ed., June 2018.

3. [3] Intel, Nios II Processor Reference Guide, April 2018.

4. [4] A. Waterman, Y. Lee, D.A. Patterson, and K. Asanović, “The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Version 2.1,” Tech. Rep. UCB/EECS-2016-118, EECS Department, University of California, Berkeley, May 2016.

5. [5] R. Höller, D. Haselberger, D. Ballek, P. Rössler, M. Krapfenbauer, and M. Linauer, “Open-Source RISC-V Processor IP Cores for FPGAs — Overview and Evaluation,” 2019 8th Mediterranean Conference on Embedded Computing (MECO), pp.1-6, June 2019. 10.1109/meco.2019.8760205

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