A Soft RISC-V Processor IP with High-performance and Low-resource consumption for FPGA

Author:

Zheng Tian1,Cai Gang1,Huang Zhihong1

Affiliation:

1. Aerospace Information Research Institute,Chinese Academy of Sciences,Beijing,China,100094

Publisher

IEEE

Reference19 articles.

1. PicoRV32 - A Size-Optimized RISC-V CPU;C Wolf,0

2. TAIGA: A new RISC-V soft-processor framework enabling high performance CPU architectural features

3. A Catalog and In-Hardware Evaluation of Open-Source Drop-In Compatible RISC-V Softcore Processors;heinz;2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig),2019

4. VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation;SpinalHDL,0

5. The Berkeley Out-of-Order Machine (BOOM): An Industry-Competitive, Synthesizable, Parameterized RISC-V Processor;celio,0

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Implementation of Floating-Point Transcendental Function Processor Based on RISC- V Architecture;2024 13th International Conference on Communications, Circuits and Systems (ICCCAS);2024-05-10

2. Performance Evaluation of PicoRV32 RISC-V Softcore for Resource-Constrained Devices;2023 IEEE Nordic Circuits and Systems Conference (NorCAS);2023-10-31

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