Test set compaction algorithms for combinational circuits

Author:

Hamzaoglu Ilker,Patel Janak H.

Publisher

ACM Press

Cited by 45 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Test Compaction Using (k, 1)-Cycle Tests;2024 IEEE 42nd VLSI Test Symposium (VTS);2024-04-22

2. Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01

3. Compact Set of Functional Broadside Tests with Fault Detection on Primary Outputs;2023 IEEE 41st VLSI Test Symposium (VTS);2023-04-24

4. Sharing of Compressed Tests Among Logic Blocks;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2023-04

5. An algorithmic approach for minimizing test power in VLSI circuits;IOP Conference Series: Materials Science and Engineering;2021-02-01

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