An algorithmic approach for minimizing test power in VLSI circuits

Abstract

Abstract Testing is an approach to check the function of the circuit or device under the test after its fabrication. To test the device, test patterns are required. The test patterns can be generated with the help of EDA tool. Those patterns having huge number of unfilled bits. The unfilled bits need to be assigned with certain logical value. This paper proposed two new algorithms. First algorithm assigns the unfilled bits with effective logical value and second algorithm change the order of test set and both algorithms aims to reduce the test power. Investigation on benchmark circuits shows that, the results of proposed algorithms effectively reduces the test power.