An algorithmic approach for minimizing test power in VLSI circuits

Author:

Poornimasre J.,Rajaguru Hari Kumar

Abstract

Abstract Testing is an approach to check the function of the circuit or device under the test after its fabrication. To test the device, test patterns are required. The test patterns can be generated with the help of EDA tool. Those patterns having huge number of unfilled bits. The unfilled bits need to be assigned with certain logical value. This paper proposed two new algorithms. First algorithm assigns the unfilled bits with effective logical value and second algorithm change the order of test set and both algorithms aims to reduce the test power. Investigation on benchmark circuits shows that, the results of proposed algorithms effectively reduces the test power.

Publisher

IOP Publishing

Subject

General Medicine

Reference15 articles.

1. Hamming distance-based test vector reordering techniques for minimizing switching activity during testing of VLSI circuits;Kuppusamy;International AMSE Journal- Modelling A

2. Functional distance based test vector reordering for low power testing of VLSI circuits;Kuppusamy,2017

3. Survey of low-power testing of VLSI circuits;Girard,2002

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