Sharing of Compressed Tests Among Logic Blocks
Author:
Affiliation:
1. School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN, USA
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Hardware and Architecture,Software
Link
http://xplorestaging.ieee.org/ielx7/92/10079225/10049462.pdf?arnumber=10049462
Reference25 articles.
1. An efficient test data reduction technique through dynamic pattern mixing across multiple fault models
2. Choosing the Right Mix of At-speed Structural Test Patterns: Comparisons in Pattern Volume Reduction and Fault Detection Efficiency
3. Test compaction for small-delay defects using an effective path selection scheme
4. Compact Test Pattern Selection for Small Delay Defect
5. Test vector decomposition-based static compaction algorithms for combinational circuits
Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01
2. Sharing of Topped-Off Compressed Test Sets Among Logic Blocks;IEEE Access;2024
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