Compact Test Pattern Selection for Small Delay Defect

Author:

Chia-Yuan Chang ,Kuan-Yu Liao ,Sheng-Chang Hsu ,Li J. C.,Jiann-Chyi Rau

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Cited by 21 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Compact pattern set generation for accelerated small delay defect testing;Results in Engineering;2024-09

2. Dynamic Test Compaction of a Compressed Test Set Shared Among Logic Blocks;IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems;2024-01

3. Testability Evaluation for Local Design Modifications;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2024-01

4. Longest Path Selection Based on Path Identifiers;IEEE Access;2024

5. Compaction of Functional Broadside Tests for Path Delay Faults Using Clusters of Propagation Lines;2023 IEEE International Test Conference (ITC);2023-10-07

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