Author:
Yiannacouras Peter,Rose Jonathan,Steffan J. Gregory
Cited by
11 articles.
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1. SPARKLE: A 1,024-Core/16,384-Thread Single FPGA Many-Core RISC-V Barrel Processor Overlay;2024 IEEE 35th International Conference on Application-specific Systems, Architectures and Processors (ASAP);2024-07-24
2. Design Exploration of RISC-V Soft-Cores through Speculative High-Level Synthesis;2022 International Conference on Field-Programmable Technology (ICFPT);2022-12-05
3. An Efficient Resource Shared RISC-V Multicore Architecture;IEICE Transactions on Information and Systems;2022-09-01
4. Efficient Resource Shared RISC-V Multicore Processor;2021 IEEE 14th International Symposium on Embedded Multicore/Many-core Systems-on-Chip (MCSoC);2021-12
5. Time-Multiplexed FPGA Overlay Architectures;ACM Transactions on Design Automation of Electronic Systems;2019-09-30