Design and algorithm for clock gating and flip-flop co-optimization-Reference-Cited by-同舟云学术

Design and algorithm for clock gating and flip-flop co-optimization

Published:2018-11-05 Issue: Volume: Page:
ISSN:
Container-title:Proceedings of the International Conference on Computer-Aided Design
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Author:

Yang Giyoung¹,Kim Taewhan¹

Affiliation:

1. Seoul National University, Seoul, Korea

Funder

Korea government (Ministry of Science and ICT)

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3240765.3240793

Reference13 articles.

1. L Benini et al. 1994. Saving power by synthesizing gated clocks for sequential circuits. IEEE Design & Test of Computors 11 4 (1994). 10.1109/54.329451 L Benini et al. 1994. Saving power by synthesizing gated clocks for sequential circuits. IEEE Design & Test of Computors 11 4 (1994). 10.1109/54.329451

2. A survey of design techniques for system-level dynamic power management

3. Rannan Fraer et al. 2008. A new paradigm for synthesis and propagation of clock gating conditions. In ACM/IEEE DAC. 10.1145/1391469.1391638 Rannan Fraer et al. 2008. A new paradigm for synthesis and propagation of clock gating conditions. In ACM/IEEE DAC. 10.1145/1391469.1391638

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