Integrated Clock Gating Analysis of TG Based D Flip-Flop for Different Technology Nodes
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Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-2761-3_9
Reference8 articles.
1. V.G. Oklobdzija, V.M. Stojanovic, D.M. Markovic, N.M. Nedovic, Digital System Clocking: High-Performance and Low-Power Aspects (Wiley, New York, 2003)
2. E. Late, A.A. Vatanjou, T. Ytterdal, S. Aunet, Comparative analysis of flip-flop architectures for subthreshold applications in 28 nm FDSOI, in 2015 Nordic Circuits and Systems Conference (NORCAS): NORCHIP and International Symposium on System-on-Chip (SoC), Oslo (2015)
3. M. Voernes, T. Ytterdal, S. Aunet, Performance comparison of 5 subthreshold CMOS flip-flops under process, voltage, and temperature variations, based on netlists from layout, in 2014 NORCHIP, Tampere (2014)
4. G. Gerosa, S. Gary, C. Dietz, D. Pham, K. Hoover, J. Alvarez, H. Sanchez, P. Ippolito, T. Ngo, S. Litch, J. Eno, J. Golab, N. Vanderschaaf, J. Kahle, A 2.2 W, 80 MHz superscalar RISC microprocessor. IEEE J. Solid-State Circ. 29, 1440–1454 (1994)
5. T. Noor, E. Salman, A novel glitch-free integrated clock gating cell for high reliability, in 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan (2019)
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