Standard Cell Layout Regularity and Pin Access Optimization Considering Middle-of-Line

Author:

Ye Wei1,Yu Bei2,Pan David Z. O.2,Ban Yong-Chan3,Liebmann Lars4

Affiliation:

1. University of Texas at Austin, Austin, TX, USA & Zhejiang University, Hangzhou, China

2. University of Texas at Austin, AUSTIN, TX, USA

3. LG Electronics, Seoul, South Korea

4. IBM Corporation, Hopewell Junction, NY, USA

Publisher

ACM

Reference24 articles.

1. Design for Manufacturing With Emerging Nanolithography

2. Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings

3. Hybrid lithography optimization with e-beam and immersion processes for 16nm 1D gridded design;Du Y.;ASPDAC,2012

4. New placement prediction and mitigation techniques for local routing congestion;Taghavi T.;ICCAD,2010

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1. Sub-10nm Standard Cell Library Design Methodology for On-Grid Pin Accesses;2024 IEEE International Symposium on Circuits and Systems (ISCAS);2024-05-19

2. Migrating Standard Cells for Multiple Drive Strengths by Routing Imitation;2024 2nd International Symposium of Electronics Design Automation (ISEDA);2024-05-10

3. Design of Digital Integrated Circuits by Improving the Characteristics of Digital Cells;Machine Learning-based Design and Optimization of High-Speed Circuits;2023-12-31

4. Pin Accessibility Improvement with Hit-Point Distribution Metrics for Sub-4nm Standard Cell;2023 IEEE 36th International System-on-Chip Conference (SOCC);2023-09-05

5. Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis;ACM/IEEE International Symposium on Low Power Electronics and Design;2022-08

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