Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis-Reference-Cited by-同舟云学术

Improving Performance and Power by Co-Optimizing Middle-of-Line Routing, Pin Pattern Generation, and Contact over Active Gates in Standard Cell Layout Synthesis

Published:2022-08 Issue: Volume: Page:
ISSN:
Container-title:ACM/IEEE International Symposium on Low Power Electronics and Design
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Author:

Chung Sehyeon¹,Jeong Jooyeon¹,Kim Taewhan¹

Affiliation:

1. Seoul National University, Republic of Korea

Publisher

ACM

Reference14 articles.

1. Chris Auth 2017 . A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects . In Proc. IEEE International Electron Devices Meeting (IEDM). Chris Auth 2017. A 10nm high performance and low-power CMOS technology featuring 3 rd generation FinFET transistors, Self-Aligned Quad Patterning, contact over active gate and cobalt local interconnects. In Proc. IEEE International Electron Devices Meeting (IEDM).

2. Improving Performance, Power, and Area by Optimizing Gear Ratio of Gate-Metal Pitches in Sub-10nm Node CMOS Designs

3. Chris Chu . 2004 . FLUTE: Fast lookup table based wirelength estimation technique. In ICCAD. Chris Chu. 2004. FLUTE: Fast lookup table based wirelength estimation technique. In ICCAD.

4. Lawrence T Clark 2016. ASAP7: A 7-nm finFET predictive process design kit. Microelectronics Journal. Lawrence T Clark 2016. ASAP7: A 7-nm finFET predictive process design kit. Microelectronics Journal.

5. Andrew B Kahng 2021. In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence . IEEE TCAD ( 2021 ). Andrew B Kahng 2021. In-Route Pin Access-Driven Placement Refinement for Improved Detailed Routing Convergence. IEEE TCAD (2021).