Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions-Reference-Cited by-同舟云学术

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Enabling Branch-Mispredict Level Parallelism by Selectively Flushing Instructions

Published:2021-10-17 Issue: Volume: Page:
ISSN:
Container-title:MICRO-54: 54th Annual IEEE/ACM International Symposium on Microarchitecture
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Author:

Eyerman Stijn¹,Heirman Wim¹,Van Den Steen Sam²,Hur Ibrahim²

Affiliation:

1. Intel, Belgium

2. Intel

Publisher

ACM

Link

https://dl.acm.org/doi/pdf/10.1145/3466752.3480045

Reference44 articles.

1. Exploiting Postdominance for Speculative Parallelization

2. Fetch-Criticality Reduction through Control Independence

3. Transparent control independence (TCI)

4. Redefining the Role of the CPU in the Era of CPU-GPU Integration

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor;IEEE Micro;2023-09

2. Simulating Wrong-Path Instructions in Decoupled Functional-First Simulation;2023 IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS);2023-04

3. Late-Stage Optimization of Modern ILP Processor Cores via FPGA Simulation;Applied Sciences;2022-11-29

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