Author:
Agarwal Mayank,Navale Nitin,Malik Kshitiz,Frank Matthew I.
Abstract
Architectures that exploit control independence (CI) promise to remove in-order fetch bottlenecks, like branch mispredicts, instruction-cache misses and fetch unit stalls, from the critical path of single-threaded execution. By exposing more fetch options, however, CI architectures also expose more performance tradeoffs. These tradeoffs make it hard to design policies that deliver good performance.This paper presents a criticality-based model for reasoning about CI architectures, and uses that model to describe the tradeoffs between gains from control independence versus increased costs of honoring data dependences. The model is then used to derive the design of a criticality-aware task selection policy that strikes the right balance between fetch-criticality and execute-criticality. Finally, the papervalidates the model by attacking branch-misprediction induced fetch-criticality through the above derived spawnpolicy. This leads to as high as 100% improvements in performance, and in the region of 40% or more improvements for four of the benchmarks where this is the main problem. Criticality analysis shows that this improvement arises due to reduced fetch-criticality.
Publisher
Association for Computing Machinery (ACM)
Reference39 articles.
1. Exploiting Postdominance for Speculative Parallelization
2. H. Akkary and M. A. Driscoll. A dynamic multithreading processor. Int'l Symp. Microarchitecture (MICRO-31):226- 236 1998. H. Akkary and M. A. Driscoll. A dynamic multithreading processor. Int'l Symp. Microarchitecture (MICRO-31):226- 236 1998.
3. Transparent control independence (TCI)
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