The Intel Programmable and Integrated Unified Memory Architecture Graph Analytics Processor

Author:

Aananthakrishnan Sriram1ORCID,Abedin Shamsul1ORCID,Cavé Vincent1ORCID,Checconi Fabio1ORCID,Bois Kristof Du2ORCID,Eyerman Stijn2ORCID,Fryman Joshua B.1,Heirman Wim2ORCID,Howard Jason1ORCID,Hur Ibrahim1ORCID,Jain Samkit1ORCID,Landowski Marek M.3ORCID,Ma Kevin1,Nelson Jarrod A.1ORCID,Pawlowski Robert1,Petrini Fabrizio4,Szkoda Sebastian3,Tayal Sanjaya5ORCID,Tithi Jesmin Jahan4ORCID,Vandriessche Yves2ORCID

Affiliation:

1. Intel Corporation, Hillsboro, OR, USA

2. Intel Corporation, Brussels, Belgium

3. Intel Corporation, 22 80-298 Gdansk, Poland

4. Intel Corporation, Santa Clara, CA, USA

5. Intel Corporation, Hillsboro, OR, 97124, USA

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Reference12 articles.

1. Overview of the next generation cray XMT;kopser;Proc Cray User Group,0

2. Automatic Sublining for Efficient Sparse Memory Accesses

3. Novel graph processor architecture, prototype system, and results

4. SIMD-X: Programming and processing of graph algorithms on GPUs;liu;Proc USENIX Annu Tech Conf,0

5. Many-Core Graph Workload Analysis

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1. Asynchronous Memory Access Unit: Exploiting Massive Parallelism for Far Memory Access;ACM Transactions on Architecture and Code Optimization;2024-09-14

2. Two-Face: Combining Collective and One-Sided Communication for Efficient Distributed SpMM;Proceedings of the 29th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Volume 2;2024-04-27

3. HotTiles: Accelerating SpMM with Heterogeneous Accelerator Architectures;2024 IEEE International Symposium on High-Performance Computer Architecture (HPCA);2024-03-02

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