Asymmetric Underlapped FinFET Based Robust SRAM Design at 7nm Node-Reference-Cited by-同舟云学术

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Asymmetric Underlapped FinFET Based Robust SRAM Design at 7nm Node

Published:2015 Issue: Volume: Page:
ISSN:
Container-title:Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015
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Author:

Goud A. Arun,Venkatesan Rangharajan,Raghunathan Anand,Roy Kaushik

Publisher

IEEE Conference Publications

Cited by 5 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Design and Analysis of 10-nm FD-SOI FinFET by Dual-Dielectric Spacers for High-Speed Switching;Lecture Notes in Electrical Engineering;2024

2. Design and Comparative Analysis of FD-SOI FinFET with Dual-dielectric Spacers for High Speed Switching Applications;Silicon;2023-11-25

3. Improvising the Switching Ratio through Low-k / High-k Spacer and Dielectric Gate Stack in 3D FinFET - a Simulation Perspective;Silicon;2020-08-03

4. Extensive Study of Underlap Length Effect for 3-D SOI FinFET to Achieve High Switching Ratio and Low Power;Silicon;2020-05-28

5. Underlapped FinFET on insulator: Quasi3D analytical model;Solid-State Electronics;2017-03

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