Author:
Kumari Vandana,Sharmetha K.,Saxena Manoj,Gupta Mridula
Funder
Joint Science Academies Panel
Indian Academy of Sciences
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference33 articles.
1. Effects of fin width on device performance and reliability of double-gate n-type FinFETs;Lin;IEEE Trans Electron Dev,2013
2. FinFETs: from devices to architectures;Bhattacharya;Adv Electron,2014
3. A compact threshold voltage model for gate misalignment effect of DG FD SOI nMOS devices considering fringing electric field effects;Sun;IEEE Trans Electron Devices,2004
4. Goud AA, Venkatesan R, Raghunathan A, Roy K. Asymmetric underlapped FinFET based robust SRAM design at 7 nm node. In: Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition; 2015. P. 659–664.
5. Nanoscale FinFET Based SRAM cell design: analysis of performance metric, process variation, underlapped FinFET and temperature effect;Raj;IEEE Circuits Syst Mag,2011
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