Design and Analysis of 10-nm FD-SOI FinFET by Dual-Dielectric Spacers for High-Speed Switching
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Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-97-0767-6_18
Reference19 articles.
1. Vadthiya N (2021) Design and deep insights into sub-10 nm spacer engineered junctionless FinFET for nanoscale applications. ECS J Solid State Sci Technol 10(1):013008. https://doi.org/10.1149/2162-8777/abddd4
2. Ryu D, Myeong I, Lee JK, Kang M, Jeon J, Shin H (2019) Investigation of gate sidewall spacer optimization from OFF-state leakage current perspective in 3-nm node device. IEEE Trans Electron Devices 66(6):2532–2537. https://doi.org/10.1109/TED.2019.2912394
3. Yamada T, Nakajima Y, Hanajiri T, Sugano T (2013) Suppression of drain-induced barrier lowering in silicon-on-insulator MOSFETs through source/drain engineering for low-operating-power system-on-chip applications. IEEE Trans Electron Devices 60(1):260–267. https://doi.org/10.1109/TED.2012.2225063
4. Vadthiya N, Narware P, Bheemudu V, Sunitha B (2020) A novel bottom-spacer ground-plane (BSGP) FinFET for improved logic and analog/RF performance. AEU Int J Electron Commun 127.https://doi.org/10.1016/j.aeue.2020.153459
5. Saremi M, Afzali-Kusha A, Mohammadi S (2012) Ground plane fin-shaped field effect transistor (GP-FinFET): a FinFET for low leakage power circuits. Microelectron Eng 95:74–82. https://doi.org/10.1016/j.mee.2012.01.009
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