Author:
Lau John H.,Ko Cheng-Ta,Peng Chia-Yu,Yang Kai-Ming,Xia Tim,Lin Puru Bruce,Chen Jean-Jou,Huang Po-Chun,Tseng Tzvy-Jang,Lin Eagle,Chang Leo,Lin Curry,Lu Winnie
Abstract
Abstract
In this investigation, the chip-last, redistribution-layer (RDL)–first, fan-out panel-level packaging (FOPLP) for heterogeneous integration is studied. Emphasis is placed on the materials, process, fabrication, and reliability of a heterogeneous integration of one large chip (10 × 10 mm2) and two small chips (7 × 5 mm2) by an FOPLP method on a 20 × 20-mm2 RDL-first substrate fabricated on a 515 × 510 mm2 temporary glass panel. Reliability test such as the drop test of the heterogeneous integration package on a printed circuit board (PCB) is performed, and test results including failure analysis are presented. Some recommendations are also provided.
Publisher
IMAPS - International Microelectronics Assembly and Packaging Society
Subject
Electrical and Electronic Engineering,Computer Networks and Communications,Electronic, Optical and Magnetic Materials
Cited by
14 articles.
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