Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework-Reference-Cited by-同舟云学术

Assessment of STT-MRAM performance at nanoscaled technology nodes using a device-to-memory simulation framework

Published:2019-07 Issue: Volume:215 Page:111009
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Garzón Esteban,De Rose Raffaele,Crupi Felice,Trojman Lionel,Lanuzza Marco

Funder

Italian Space Agency

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference21 articles.

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4. Compact modeling of STT-MTJ devices;Xu;Solid State Electron.,2014

5. Novel metallization processes for sub-100 nm magnetic tunnel junction devices;Cao;Microelectron. Eng.,2019

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3. Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages;2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS);2023-02-27

4. An Approach towards Designing Logic Locking Using Shape-Perpendicular Magnetic Anisotropy-Double Layer MTJ;Electronics;2023-01-17

5. Exploiting TFET-based technology for energy-efficient STT-MRAM cells;INT J APPL ELECTROM;2023