Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages-Reference-Cited by-同舟云学术

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Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages

Published:2023-02-27 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE 14th Latin America Symposium on Circuits and Systems (LASCAS)
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Author:

Pérez Santiago S.¹,Bedoya Alessandro¹,Prócel Luis Miguel¹,Taco Ramiro¹

Affiliation:

1. Instituto de Micro y Nanoelectrónica, Universidad San Francisco de Quito,Quito,Ecuador

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10108078/10108098/10108163.pdf?arnumber=10108163

Reference19 articles.

1. A Scaling Roadmap and Performance Evaluation of In-Plane and Perpendicular MTJ Based STT-MRAMs for High-Density Cache Memory

2. Bottom Oxide Bulk FinFETs Without Punch-Through-Stopper for Extending Toward 5-nm Node

3. Digital and analog TFET circuits: Design and benchmark

4. Compact modeling of STT-MTJ for SPICE simulation

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