Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking-Reference-Cited by-同舟云学术

Assembly technology development and failure analysis for three-dimensional integrated circuit integration with ultra-thin chip stacking

Published:2016-04 Issue: Volume:156 Page:24-29
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Lee Chang-Chun,Lin Yu-Min,Hsieh Chia-Ping,Liou Yan-Yu,Zhan Chau-Jie,Chang Tao-Chih,Wang Chien-Ping

Funder

National Center for High-performance Computing (NCHC)

Ministry of Science and Technology, Taiwan (MOST)

EORL/ITRI

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference23 articles.

1. Proceeding of 61th IEEE Electronic Components and Technology Conference, Lake Buena Vista, FL;Yoon,2011

2. Experimental characterization of coaxial through silicon vias for 3D integration

3. Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

4. Effect of wafer thinning methods towards fracture strength and topography of silicon die

5. Investigations of the influence of dicing techniques on the strength properties of thin silicon

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