Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14nm nodes FinFET technology

Author:

Wang GuileiORCID,Qin Changliang,Yin Huaxiang,Luo Jun,Duan Ningyuan,Yang Ping,Gao Xingyu,Yang Tao,Li Junfeng,Yan Jiang,Zhu Huilong,Wang Wenwu,Chen Dapeng,Ye Tianchun,Zhao Chao,Radamson Henry H.

Funder

National S&T Major Project 02

Microelectronics Devices & Bulk Si FinFET Integrated Technology

Institute of Microelectronics

Chinese Academy of Sciences

Youth Innovation Promotion Association of CAS

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference17 articles.

1. Migrating from planar to FinFET for further CMOS scaling: SOI or bulk?;Chiarella,2009

2. A 22nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors;Auth,2012

3. A 14nm logic technology featuring 2nd-generation FinFET, air-gapped interconnects, self-aligned double patterning and a 0.0588μm2 SRAM cell size;Natarajan,2014

4. Optimization of SiGe selective epitaxy for source/drain engineering in 22nm node complementary metal-oxide semiconductor (CMOS);Wang;J. Appl. Phys.,2013

5. Integration of highly-strained SiGe materials in 14nm and beyond nodes FinFET technology;Wang;Solid State Electron.,2015

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