Improved electrical characteristics of high-k gated MOSFETs with post-growth treatment on interfacial layer-Reference-Cited by-同舟云学术

Improved electrical characteristics of high-k gated MOSFETs with post-growth treatment on interfacial layer

Published:2015-04 Issue: Volume:138 Page:81-85
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Ruan Dun-Bao,Chang-Liao Kuei-Shu,Li Chen-Chien,Lu Chun-Chang,Liao Yu-Liang,Chen Li-Ting,Li Yan-Lin,Fu Chung-Hao,Hsieh Tsung-Lin

Funder

Ministry of Science and Technology, Taiwan

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference25 articles.

1. Physically based quantum-mechanical compact model of MOS devices substrate-injected tunneling current through ultrathin (EOT /spl sim/ 1 nm) SiO/sub 2/ and high-/spl kappa/ gate stacks

2. Charge trapping properties in TiO[sub 2]∕HfSiO∕SiO[sub 2] gate stacks probed by scanning capacitance microscopy

3. Epitaxial SrO interfacial layers for HfO2–Si gate stack scaling

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