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Vertically-stacked gate-all-around polysilicon nanowire FETs with sub-μm gates patterned by nanostencil lithography

Published:2012-10 Issue: Volume:98 Page:355-358
ISSN:0167-9317
Container-title:Microelectronic Engineering
language:en
Short-container-title:Microelectronic Engineering

Author:

Sacchetto Davide,Xie Shenqi,Savu Veronica,Zervas Michael,De Micheli Giovanni,Brugger Jürgen,Leblebici Yusuf

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

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3. H., Iwai, Roadmap for 22nm and beyond (invited paper). Microelectronic Engineering 86 (7–9) (2009) 1520–1528.

4. Fabrication and characterization of vertically stacked gate-all-around si nanowire fet arrays. In: Solid State Device Research Conference, ESSDERC ’09;Sacchetto;Proceedings of the European.,2009

5. High throughput nanofabrication of silicon nanowire and carbon nanotube tips on afm probes by stencil-deposited catalysts;Engstrom;Nano Letters,2011

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