Author:
Yeh Wen-Kuan,Chen Po-Ying,Gan Kwang-Jow,Wang Jer-Chyi,Lai Chao Sung
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference9 articles.
1. Akasaka Y, Shiraishi K, Umezawa N, Ogawa O, Kasuya T, Chikyow T, et al. A novel remote reactive sink layer technique for the control of N and O concentrations in metal/high-k gate stacks. In: Proceeding of Symposium VLSI Technology; 2006. p. 164–5.
2. Ren C, Yu HY, Wang XP, Ma HH, Chan DSH, Li M-F, et al. Thermally robust TaTbxN metal gate electrode for n-MOSFETs applications. IEEE Electron Device Letters 2004:75–77.
3. Kang CY, Young CD, Huang J, Kirsch P, Heh D, Sivasubramani P, et al. The impact of la-doping on the reliability of low VTH high-k/metal gate nMOSFETs under various gate stress conditions. In: Proceedings of IEDM technical digestive; 2008. p. 15–8.
4. Sato M, Umezawa N, Shimokawa J, Arimura H, Sugino S, Tachibana A, et al. Physical model of the PBTI and TDDB of la incorporated HfSiON gate dielectrics with pre-existing and stress-induced defects. In: Proceedings of IEDM technical digestive; 2008. p. 45–8.
5. Kita K, Toriumi A. Intrinsic origin of electric dipoles formed at high-k/SiO2 interface. In: Proceedings of IEDM technical digestive; 2008. p. 1–4.
Cited by
2 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献
1. On the current conduction mechanisms of CeO2/La2O3 stacked gate dielectric;Microelectronics Reliability;2014-06
2. Advanced methodology for electrical characterization of metal/high-k interfaces;Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena;2014-05