Effects of TSVs (through-silicon vias) on thermal performances of 3D IC integration system-in-package (SiP)

Author:

Lau John H.,Yue Tang Gong

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference34 articles.

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3. Kumagai K, Yoneda Y, Izumino H, Shimojo H, Sunohara M, Kurihara T. A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection. In: IEEE proceedings of electronic components and technology conf, Orlando, FL; May 2008. p. 571–6.

4. Sunohara M, Tokunaga T, Kurihara T, Higashi M. Silicon interposer with TSVs (Through Silicon Vias) and fine multilayer wiring. In: IEEE proceedings of electronic components and technology conf, Orlando, FL; May 2008. p. 847–52.

5. Lee HS, Choi Y-S, Song E, Choi K, Cho T, Kang S. Power delivery network design for 3D SIP integrated over silicon interposer platform. In: IEEE proceedings of electronic components and technology conf, Reno, NV; May 2007. p. 1193–8.

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