Solder joint and trace line failure simulation and experimental validation of fan-out type wafer level packaging subjected to drop impact

Author:

Chou Chan-Yen,Hung Tuan-Yu,Yang Shin-Yueh,Yew Ming-Chih,Yang Wen-Kun,Chiang Kuo-Ning

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference12 articles.

1. JEDEC Solid State Technology Association, JESD22-B110: Subassembly Mechanical Shock; 2001.

2. JEDEC Solid State Technology Association, JESD22-B111: Board level drop test method of component for handheld electronics products; 2003.

3. Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis;Yew;Microelectron Reliab,2007

4. The solder on rubber (SOR) Interconnection design and its reliability assessment based on shear strength test and finite element analysis;Yew;Microelectron Reliab,2006

5. Design, analysis and development of novel three-dimensional stacking WLCSP;Yuan;IEEE Trans Adv Packag,2005

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