Reliability assessment for solders with a stress buffer layer using ball shear strength test and board-level finite element analysis

Author:

Yew Ming-Chih,Chou Chan-Yen,Chiang Kuo-Ning

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference13 articles.

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3. Gonzalez M et al. An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration. In: Proceedings of the 53rd electronic components and technology conference; 2003. p. 857–63.

4. Kazama A, Satoh T, Yamaguchi Y, Anjoh I, Nishimura A. Development of low-cost and highly reliable wafer process package. In: Proceedings of the 51st electronic components and technology conference; 2001. p. 40–6.

5. Ultrathin wafer level chip size package;Badihi;IEEE Trans Adv Pack,2000

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