Author:
Yew Ming-Chih,Chou Chan-Yen,Chiang Kuo-Ning
Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference13 articles.
1. Flip chip technologies;Lau,1995
2. Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability;Lau;IEEE Trans Electron Pack M,2002
3. Gonzalez M et al. An analysis of the reliability of a wafer level package (WLP) using a silicone under the bump (SUB) configuration. In: Proceedings of the 53rd electronic components and technology conference; 2003. p. 857–63.
4. Kazama A, Satoh T, Yamaguchi Y, Anjoh I, Nishimura A. Development of low-cost and highly reliable wafer process package. In: Proceedings of the 51st electronic components and technology conference; 2001. p. 40–6.
5. Ultrathin wafer level chip size package;Badihi;IEEE Trans Adv Pack,2000
Cited by
9 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献