Subject
Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials
Reference32 articles.
1. International Technology Roadmap of Semiconductors (ITRS). .
2. Boselli G. Analysis of ESD protection components in 65nm CMOS technology: scaling perspective and impact on ESD design window. In: EOS/ESD symposium; 2005. p. 43–52.
3. Trends and challenges to ESD and latch-up designs for nanometer CMOS technologies;Boselli;Microelectron Reliab,2005
4. Gauthier R. Evaluation of diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13m CMOS logic technology. In: EOS/ESD symposium; 2001. p. 205–15.
5. Analysis of failure mechanism on gate-silicided and gate-non-silicided ESD NMOSFETs in a 65nm bulk CMOS technology;Li;IPFA,2006
Cited by
21 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献