Enhancing ESD Performance of FinSCRs: Engineering Schemes to Address Current Localization and Failure Current Scalability
Author:
Affiliation:
1. Department of Electronic Systems Engineering, Advanced Nanoelectronics Device and Circuit Research Group, Indian Institute of Science, Bangalore, India
Publisher
Institute of Electrical and Electronics Engineers (IEEE)
Subject
Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials
Link
http://xplorestaging.ieee.org/ielx7/16/10194493/10183867.pdf?arnumber=10183867
Reference35 articles.
1. ESD Protection Design Overview in Advanced SOI and Bulk FinFET Technologies
2. Novel SCR structure for power supply protection in FinFET technology
3. Design and optimization of ESD lateral NPN device in 14nm FinFET SOI CMOS technology
4. Low-Capacitance SCR for On-Chip ESD Protection with High CDM Tolerance in 7nm Bulk FinFET Technology
5. A low-leakage SCR design using trigger-PMOS modulations for ESD protection;morishita;Proc Electrical Overstress/Electrostatic Discharge (EOS/ESD) Symp,2007
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