A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect-Reference-Cited by-同舟云学术

A study of Cu/Low-k stress-induced voiding at via bottom and its microstructure effect

Published:2006-09 Issue:9-11 Volume:46 Page:1673-1678
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Wang Robin C.J.,Lee C.C.,Chen L.D.,Wu Kenneth,Chang-Liao K.S.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference7 articles.

1. Ogawa ET, McPherson JW, Rosal JA, Dickerson KJ, Chiu TC, Tsung LY, Jain MK, Bonifield TD, Ondrusek JC, McKee WR, et al. Stress-induced voiding under vias connected to wide Cu metal leads. In: IEEE Inter. Reliability Physics Symposium, 2002, p. 312–21.

2. Gan D, Wang G, Ho PS. Effects of dielectric material and linewidth on thermal stress of Cu line structures. In: Inter. Interconnect Technology Conf., 2002, p. 271–3.

3. Okada N, Matsubara Y, Kimura H, Aizawa H, Nakamura N. Thermal stress of 140 nm-width Cu damascene interconnects. In: Inter. Interconnect Technology Conf., 2002, p. 136–8.

4. Lim YK, Lim YH, Kamat NR, See A, Lee TJ, Pey KL, et al. Stress-induced voiding beneath vias with wide copper metal leads. In: IEEE Inter. Physics and Failure analysis Symposium, 2004, p. 103–6.

5. Glasow AV, Fischer AH, Hierlemann M, Penke S, Ungar F, et al. Geometrical aspects of stress-induced voiding in Cu interconnects. In: Advanced Metallization Conference, 2002, p. 161–7.

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