Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array-Reference-Cited by-同舟云学术

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Built-In Self-Test Methodology With Statistical Analysis for Electrical Diagnosis of Wearout in a Static Random Access Memory Array

Published:2016-07 Issue:7 Volume:24 Page:2521-2534
ISSN:1063-8210
Container-title:IEEE Transactions on Very Large Scale Integration (VLSI) Systems
language:
Short-container-title:IEEE Trans. VLSI Syst.

Author:

Kim Woongrae,Chen Chang-Chih,Kim Dae-Hyun,Milor Linda

Funder

Defense Advanced Research Projects Agency

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Hardware and Architecture,Software

Link

http://xplorestaging.ieee.org/ielx7/92/7498705/07401105.pdf?arnumber=7401105

Cited by 9 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An in-Array Build-In Self-Test Scheme for Embedded SRAM Array;IEEE Transactions on Circuits and Systems II: Express Briefs;2024-08

2. A Simulation Approach to Analyze Bridge-Defects in a 6T-SRAM Bit Cell;2022 6th IEEE Electron Devices Technology & Manufacturing Conference (EDTM);2022-03-06

3. Bridge-Defect Prediction in SRAM Circuits Using Random Forest, XGBoost, and LightGBM Learners;2021 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD);2021-09-27

4. Optimal Accelerated Test Framework for Time-Dependent Dielectric Breakdown Lifetime Parameter Estimation;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2020-12

5. Extraction of wearout model parameters using on-line test of an SRAM;Microelectronics Reliability;2020-11

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