A single event upset tolerant latch design-Reference-Cited by-同舟云学术

A single event upset tolerant latch design

Published:2018-09 Issue: Volume:88-90 Page:909-913
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Wang Haibin^ORCID,Dai Xixi,Wang Yangsheng,Nofal Issam,Cai Li,Shen Zicai,Sun Wanxiu,Bi Jinshun,Li Bo^ORCID,Guo Gang,Chen Li,Baeg Sang

Funder

Fundamental Research Funds for the Central Universities

NSFC

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference21 articles.

1. Basic mechanisms and modeling of single-event upset in digital microelectronics;Dodd;IEEE Trans. Nucl. Sci.,2003

2. A CMOS triple inter-locked latch for SEU insensitivity design;Li;IEEE Trans. Nucl. Sci.,2014

3. A highly reliable SEU hardened latch and high performance SEU hardened flip-flop;Islam;IEEE ISQED,2012

4. SEU tolerant latch based on error detection;She;IEEE Trans. Nucl. Sci.,2012

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