Design and analysis of a SET tolerant single-phase clocked double-tail dynamic comparator

Author:

Wu Hao,Jin Gang,Zhuang Yiqi

Funder

Overseas Expertise Introduction Project for Discipline Innovation

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Efficient Design of a Double Tail Dynamic Comparator for High Speed and Low Power Applications in 90nm Technology;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

2. Spatiotemporal variation of the carbon footprint of tobacco production from 2004 to 2017 in China;Frontiers in Environmental Science;2024-04-18

3. A Single-Event Transient (SET) Tolerant Dynamic Bias Comparator in 65-nm CMOS;2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS);2023-08-06

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