Method to estimate profile of threshold voltage degradation in MOSFETs due to electrical stress-Reference-Cited by-同舟云学术

Method to estimate profile of threshold voltage degradation in MOSFETs due to electrical stress

Published:2018-09 Issue: Volume:88-90 Page:186-190
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Yun Yeohyeok,Seo Ji-Hoon,Son Donghee,Kang Bongkoo

Funder

Samsung

Ministry of Science, ICT and Future Planning

Institute for Information & communications Technology Promotion

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference28 articles.

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4. Interface state creation and charge trapping in the medium-to-high gate voltage range (Vd/2 ≥ Vg ≥ Vd) during hot-carrier stressing of n-MOS transistors;Doyle;IEEE Trans. Electron Devices,1990

5. Impact of off-state stress and negative bias temperature instability on degradation of nanoscale pMOSFET;Lee;IEEE Electron Device Lett.,2012

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1. Capacitance Method for Identifying Degradation due to Electrical Stress in MOSFETs;e-Journal of Surface Science and Nanotechnology;2022-07-07

2. Hot Carrier Degradation in MOSFETs at Cryogenic Temperatures Down to 4.2 K;IEEE Transactions on Device and Materials Reliability;2021-12

3. The properties, effect and extraction of localized defect profiles from degraded FET characteristics;2021 IEEE International Reliability Physics Symposium (IRPS);2021-03

4. Lateral Capacitance–Voltage Method of NanoMOSFET for Detecting the Hot Carrier Injection;Applied Sciences;2020-11-09

5. Channel-length dependence of the generation of interface states and oxide-trapped charges on drain avalanche hot carrier degradation of HfSiON/SiO2 p-channel MOSFETs with strained Si/SiGe channel;Japanese Journal of Applied Physics;2020-04-06