1. Cycling endurance optimization scheme for 1 Mb STT-MRAM in 40 nm technology;Yu,2013
2. A 64Mb MRAM with clamped-reference and adequate-reference schemes;Tsuchida,2010
3. Embedded STT-MRAM in 28-nm FDSOI logic process for industrial MCU/IoT application;Lee,2018
4. 7.2 4Mb STT-MRAM-based cache with memory-access-aware power optimization and write-verify-write/read-modify-write scheme;Noguchi;ISSCC,2016
5. 7.5 A 3.3ns-access-time 71.2 μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture;Noguchi,2015