Design space exploration and power optimization of STT MRAM using trimmed fin Asymmetric FinFET-Reference-Cited by-同舟云学术

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Design space exploration and power optimization of STT MRAM using trimmed fin Asymmetric FinFET

Published:2024-07 Issue: Volume:149 Page:106238
ISSN:1879-2391
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Kumar Ashok,Rajpoot Jagadish,Verma Shivam^ORCID

Funder

University Grants Commission South Eastern Regional Office

University Grants Commission

Banaras Hindu University

Banaras Hindu University Indian Institute of Technology Varanasi

Publisher

Elsevier BV

Reference30 articles.

1. Spintronics: a spin-based electronics vision for the future;Wolf;Science,2001

2. Magnetic Memory Fundamentals and Technology;Tang,2010

3. A survey of spintronic architectures for processing-in-memory and neural networks;Umesh;J. Syst. Archit.,2019

4. CSME: a novel cycle-sensing margin enhancement scheme for high yield STT-MRAM;Cai;Microelectron. Reliab.,2020

5. A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM;Zhou;Microelectron. Reliab.,2020

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Characterizing parameter variations for enhanced performance and adaptability in 3 nm MBCFET technology;Microelectronics Journal;2024-09

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