A novel BIST for monitoring aging/temperature by self-triggered scheme to improve the reliability of STT-MRAM

Author:

Zhou Y.,Cai H.,Zhang M.,Naviner L.A.B.,Yang J.

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference39 articles.

1. The emergence of spin electronics in data storage;Chapper;Nature Mater,2007

2. A 1-Mb 28-nm 1T1MTJ STT-MRAM with single-cap offset-cancelled sense amplifier and in situ self-write-termination;Dong;IEEE J. Solid State Circuits,2019

3. CMOS-embedded STT-MRAM arrays in 2x nm nodes for GP-MCU applications, 2017 Sym;Shum;VLSI Tech.,2017

4. 45nm low power CMOS logic compatible embedded STT MRAM utilizing a reverse-connection 1T/1MTJ cell;Lin,2009

5. Highly scalable STT-MRAM with MTJs of top-pinned structure in 1T/1MTJ cell;Lee,2010

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1. Design space exploration and power optimization of STT MRAM using trimmed fin Asymmetric FinFET;Microelectronics Journal;2024-07

2. On Gate Flip Errors in Computing-In-Memory;2024 Design, Automation & Test in Europe Conference & Exhibition (DATE);2024-03-25

3. Spin Transfer Torque Magnetic Random Access Memory With Built-in-Self-Trimming After-Test Writing Strategy;IEEE Transactions on Magnetics;2023-11

4. Reliability of Computing-In-Memories: Threats, Detection Methods, and Mitigation Approaches;2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT);2023-10-03

5. An On-Line Aging Detection and Tolerance Framework for Improving Reliability of STT-MRAMs;Proceedings of the 28th Asia and South Pacific Design Automation Conference;2023-01-16

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