Substrate-engineered GGNMOS for low trigger voltage ESD in 65nm CMOS process-Reference-Cited by-同舟云学术

Substrate-engineered GGNMOS for low trigger voltage ESD in 65nm CMOS process

Published:2011-12 Issue:12 Volume:51 Page:2124-2128
ISSN:0026-2714
Container-title:Microelectronics Reliability
language:en
Short-container-title:Microelectronics Reliability

Author:

Ma Fei,Han Yan,Song Bo,Dong Shurong,Miao Meng,Zheng Jianfeng,Wu Jian,Zhu Kehan

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Surfaces, Coatings and Films,Safety, Risk, Reliability and Quality,Condensed Matter Physics,Atomic and Molecular Physics, and Optics,Electronic, Optical and Magnetic Materials

Reference13 articles.

1. Speed optimized diode-triggered SCR (DTSCR) for RF ESD protection of ultra-sensitive IC nodes in advanced technologies;Mergens;IEEE Trans Dev Mater Reliab,2005

2. Substrate-triggered GGNMOS in 65nm CMOS process for ESD application;Song;Electron Lett,2010

3. Investigation of LOCOS- and polysilicon-bound diodes for robust electrostatic discharge (ESD) applications;Li;IEEE Trans Electron Dev,2010

4. Miller J, Stockinger M, Khazhinsky M, Etherton M. SPICE-based ESD protection design utilizing diodes and active MOSFET rail clamp circuits. In: Proc EOS/ESD symp; 2007.

5. ESD in silicon integrated circuits;Amerasekera,2002

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