Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-µm 5 V/18 V CDMOS process

Author:

Zhang Wenjie,Yang Liu,Wang Yang,Jin Xiangliang

Funder

State Key Program of National Natural Science of China

National Natural Science Foundation of China

Hunan Provincial Natural Science Fund for Distinguished Young Scholars

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference26 articles.

1. A new method to estimate failure temperatures of semiconductor devices under electrostatic discharge stresses;Miao;IEEE Electron Device Lett,2016

2. Design, fabrication and test of novel LDMOS-SCR for improving holding voltage;Liu;Solid-State Electronics,2014

3. Robust lateral double-diffused MOS with interleaved bulk and source for high-voltage electrostatic discharge protection;Wang;Iet Power Electronics,2015

4. Pickup impact on high voltage impact on high voltage multi-finger LDMOS_SCR with low trigger voltage and high failure current;Liu;Solid-State Electronics,2015

5. Whole-chip ESD protection design with efficient VDD-to-VSS ESD clamp circuits for submicron CMOS VLSI;Ker;IEEE Trans Electron Devices,1999

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