Robust lateral double‐diffused MOS with interleaved bulk and source for high‐voltage electrostatic discharge protection
Author:
Affiliation:
1. School of Physics and OptoelectronicsXiangtan UniversityXiangtanHunan411105People's Republic of China
2. Hunan Engineering Laboratory for MicroelectronicsOptoelectronics and System on a ChipXiangtanHunan411105People's Republic of China
Funder
National Natural Science Foundation of China
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://onlinelibrary.wiley.com/doi/pdf/10.1049/iet-pel.2014.0763
Reference20 articles.
1. Research of a novel temperature adaptive gate driver for power metal‐oxide semiconductor;Zhuang H.;IET Power Electron.,2013
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3. Novel technique for lateral high‐voltage totem‐pole power devices
4. ESD design challenges in state‐of‐the‐art analog technologies;Boselli G.;Microelectron. Reliab.,2012
5. New layout arrangement to improve ESD robustness of large‐array high‐voltage nLDMOS;Chen W.Y.;IEEE Electron Device Lett.,2010
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