Pickup impact on high-voltage multifinger LDMOS–SCR with low trigger voltage and high failure current-Reference-Cited by-同舟云学术

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Pickup impact on high-voltage multifinger LDMOS–SCR with low trigger voltage and high failure current

Published:2015-12 Issue: Volume:114 Page:9-13
ISSN:0038-1101
Container-title:Solid-State Electronics
language:en
Short-container-title:Solid-State Electronics

Author:

Yang Liu,Jin Xiangliang,Wang Yang,Zhou Acheng

Funder

State Key Program of National Natural Science of China

National Natural Science Foundation of China

Program for New Century Excellent Talents in University of Ministry of Education of China

Publisher

Elsevier BV

Subject

Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials

Reference14 articles.

1. Park JY, Song JK, Jang CS, Son YS, Kim DW. Analysis and modeling of a low voltage triggered SCR ESD protection clamp with the very fast transmission line pulse measurement. In: Quality electronic design (ISQED), international symposium; 2010. p. 206–10.

2. Huo MX, Ding KB, Han Y, Dong SR, Du XY, Huang DH, et al. Effects of process variation on turn-on voltages of a multi-finger gate-coupled NMOS ESD protection device. In: physical and failure analysis of integrated circuits, IPFA IEEE international symposium; 2009. p. 832–6.

3. A novel SCR ESD protection for triple well CMOS technologies;Nikolaidis;Electron Dev Lett, IEEE,2001

4. Investigation of the shift of hot spot in lateral diffused LDMOS under ESD conditions;Qian;Microelectron Reliab,2010

5. Review on the ESD robustness of drain-extended MOS devices;Shrivastava;IEEE Trans Dev Mater Reliab,2012

Cited by 3 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. A Silicon on Nothing LDMOS with Two Air Pillars in Gate Insulator for Power Applications;Silicon;2020-01-02

2. Design and analysis of different trigger techniques for ESD clamp circuit in 0.5-µm 5 V/18 V CDMOS process;Solid-State Electronics;2017-09

3. Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process;IEICE Transactions on Electronics;2016

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