Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process-Reference-Cited by-同舟云学术

Optimization on Layout Strategy of Gate-Grounded NMOS for On-Chip ESD Protection in a 65-nm CMOS Process

Published:2016 Issue:5 Volume:E99.C Page:590-596
ISSN:0916-8524
Container-title:IEICE Transactions on Electronics
language:en
Short-container-title:IEICE Trans. Electron.

Author:

LU Guangyi¹,WANG Yuan¹,ZHANG Xing¹

Affiliation:

1. Institute of Microelectronics, Peking University

Publisher

Institute of Electronics, Information and Communications Engineers (IEICE)

Subject

Electrical and Electronic Engineering,Electronic, Optical and Magnetic Materials

Link

https://www.jstage.jst.go.jp/article/transele/E99.C/5/E99.C_590/_pdf

Reference27 articles.

1. [1] A. Amerasekera, C. Duvvury, W. Anderson, H. Gieser, and S.Ramaswamy, ESD in silicon integrated circuits, John Wiley & Sons, 2002.

2. [2] P. Tan, I. Manna, Y. Tan, K. Lo, and P. Li, “A study of high current characteristics of devices in a 0.13µm CMOS technology,” Proc. EOS/ESD Symp., pp.186-193, Sept. 2002.

3. [3] J. Li, H. Li, R. Barnes, and E. Rosenbaum, “Comprehensive study of drain breakdown in MOSFETs,” IEEE Trans. Electron Devices, vol.52, no.6, pp.1180-1186, June 2005.

4. [4] G. Meneghesso, J.R.M. Luchies, F.G. Kuper, and A.J. Mouthaan, “Turn-on speed of grounded gate NMOS ESD protection transistors,” Microelectron. Reliab., vol.36, no.11/12, pp.1735-1738, 1996.

5. [5] V.A. Vashchenko, J.B. Martynov, and V.F. Sinkevitch, “Electrical filamentation in GGMOS protection structures,” Proc. EOS/ESD Symp., pp.330-336, Sept. 1997.

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