A Silicon on Nothing LDMOS with Two Air Pillars in Gate Insulator for Power Applications
Author:
Publisher
Springer Science and Business Media LLC
Subject
Electronic, Optical and Magnetic Materials
Link
http://link.springer.com/content/pdf/10.1007/s12633-019-00359-3.pdf
Reference20 articles.
1. Qiao M, Li Y, Zhou X, Li Z, Zhang B (Jul. 2014) A 700-V junction-isolated triple RESURF LDMOS with n- type top layer. IEEE Electron Device Lett 35(7):774–776
2. Yang L, Wang Y, Zhou A, Jin X (2015) Design, fabrication and test of novel LDMOS-SCR for improving holding voltage. Solid-State Electronics 103:122–126
3. F. van Rijs, “Status and trends of silicon LDMOS base station PA technologies to go beyond 2.5 GHz applications,” in Proc. IEEE Radio Wireless Symp.,vol 54, pp. 69–72, 2008
4. Meng-tian Bao, Ying Wang,” Improving breakdown voltage and self-heating effect for SiC LDMOS with double L-shaped buried oxide layers”Superlattices and Microstructures, Volume 102, p.p 147–154, 2017
5. Rupendra Kumar Sharma, Mridula Gupta, R.S. Gupta,” Two-dimensional analytical subthreshold model of graded channel DG FD SOI n-MOSFET with gate misalignment effect” Superlattices and Microstructures. vol.45, pp. 91–104, 2009
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