Substrate-triggered GGNMOS in 65 nm CMOS process for ESD application
Author:
Publisher
Institution of Engineering and Technology (IET)
Subject
Electrical and Electronic Engineering
Link
https://digital-library.theiet.org/content/journals/10.1049/el.2010.0205?crawler=true&mimetype=application/pdf
Reference6 articles.
1. Analysis of 65 nm technology grounded-gate NMOS for on-chip ESD protection applications
2. Substrate-triggered technique for on-chip ESD protection design in a 0.18-μm salicided CMOS process
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