1. Impact of SOI and Si–GeOI and GeOI substrates on CMOS compatible tunnel FET performance;Mayer,2008
2. Double-gate strained heterostructure tunneling FET (TFET) with record high drive currents and less than 60mV/dec subthreshold slope;Krishnamohan,2008
3. Fabrication, characterization, and physics of III-V heterojunction tunneling field effect transistors (H-TFET) for steep sub-threshold swing;Dewey,2011
4. Atomistic full-band design study of inas band-to-band tunneling field-effect transistors;Luisier;IEEE Electron Device Lett,2009
5. Low-voltage tunnel transistors for beyond CMOS logic;Seabaugh;Proc IEEE,2010