Author:
Chan Mansun,Su Pin,Wan Hui,Lin Chung-Hsun,Fung Samuel K.-H.,Niknejad Ali M.,Hu Chenming,Ko Ping K.
Subject
Materials Chemistry,Electrical and Electronic Engineering,Condensed Matter Physics,Electronic, Optical and Magnetic Materials
Reference26 articles.
1. Fung SKH, Khare M, Schepis D, Lee W-H, Ku SH, Park H, et al. Gate length scaling accelerated to 30 nm regime using ultra-thin film PD-SOI technology. In: 2001 IEEE International Electron Devices Meeting Technical Digest. p. 629–32
2. Concise analytical model for deep submicron n-channel metal-oxide-semiconductor devices with consideration of energy transport;Ma;Jpn. J. Appl. Phys.,1994
3. A physical charge-based model for non-fully depleted SOI MOSFET’s and its use in assessing floating-body effects in SOI CMOS circuits;Suh;IEEE Trans. Electron Dev.,1995
4. Pin Su. An International Standard Model for SOI Circuit Design. PhD dissertation, Department of EECS, University of California at Berkeley, Memorandum No. UCB/ERL M02/40, December 2002
5. http://www.eigroup.org/cmc
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